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Ordering number : ENA1636
LC87F7DJ2B
Overview
CMOS IC FROM 192K byte, RAM 8K byte on-chip
8-bit 1-chip Microcontroller
The SANYO LC87F7DJ2B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 192K-byte flash ROM (onboard programmable), 8K-byte RAM, an on-chip debugger, an LCD controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-ofday clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, two UART interface (full duplex), a 12-bit 15-channel AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, two infrared remote controller receiver function, and a 31-source 10-vector interrupt feature.
Features
Flash ROM * Capable of on-board-programming with a wide range of souce voltages: 3.0 to 5.5V * Block-erasable in 2-byte units * 196608 x 8 bits RAM * 8192 x 9 bits Minimum Bus Cycle Time * 66.6ns (15MHz) VDD=3.0 to 5.5V * 125ns (8MHz) VDD=2.5 to 5.5V * 250ns (4MHz) VDD=2.2 to 5.5V Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.0.06
D2409HKIM 20091203-S00001 No.A1636-1/26
LC87F7DJ2B
Minimum Instruction Cycle Time (tCYC) * 200ns (15MHz) VDD=3.0 to 5.5V * 375ns (8MHz) VDD=2.5 to 5.5V * 750ns (4MHz) VDD=2.2 to 5.5V Ports * Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units 29 (P0n, P1n, P70 to P73, P8n, XT2) * Normal withstand voltage input port 1 (XT1) * LCD ports Segment output 54 (S00 to S53) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports 54(P3n, PAn, PBn, PCn, PDn, PEn, PFn) Input ports 7 (PLn) * Dedicated oscillator ports 2 (CF1, CF2) * Reset pin 1 (RES) * Power pins 6 (VSS1 to VSS3, VDD1 to VDD3) LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty x 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Small Signal Detection (MIC signals etc) 1) Counts pulses with the level which is greater than a preset value 2) 2-bit counter Timers * Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers) * Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) * Timer 8: 16-bit timer Mode 0: 8-bit timer with an 8-bit prescaler x 2 channels Mode 1: 16-bit timer with an 8-bit prescaler * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes * Day and time counter 1) Using with a base timer, it can be used as 65000 day + minute + second counter.
No.A1636-2/26
LC87F7DJ2B
High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART1 * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2-bit in continuous data transmission) * Built-in baudrate generator UART2 * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2-bit in continuous data transmission) * Built-in baudrate generator AD Converter: 12 bits x 15 channels PWM: Multi frequency 12-bit PWM x 2 channels Remote Control Receiver Circuit1 1) Noise rejection function (Units of noise rejection filter: about 120s, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). 4) X'tal HOLD mode release function Remote Control Receiver Circuit2 1) Noise rejection function (Units of noise rejection filter: about 120s, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of half-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). 4) X'tal HOLD mode release function Watchdog Timer * External RC watchdog timer * Interrupt and reset signals selectable Clock Output Function 1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Can output oscillation clock of sub clock.
No.A1636-3/26
LC87F7DJ2B
Interrupts * 31 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4/remote control receiver1 INT3/base timer/INT5/remote control receiver2 T0H/INT6 T1L/T1H/INT7 SIO0/UART1 receive/UART2 receive/T8L/T8H SIO1/UART1 transmit/UART2 transmit ADC/MIC/T6/T7/PWM4/PWM5 Port 0/T4/T5 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. * IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the diagram above). Subroutine Stack Levels: 4096 levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * RC oscillation circuit (internal): For system clock * CF oscillation circuit: For system clock, with internal Rf and external Rd * Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd * Frequency variable RC oscillation circuit (internal): For system clock 1) Adjustable in 4% (typ.) step from a selected center frequency. 2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference. System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). System Clock Multiplier Function * Allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system clock. Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation.) 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt
Continued on next page.
No.A1636-4/26
LC87F7DJ2B
Continued from preceding page.
* HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X'tal, and frequency variable RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and the remote control receiver circuit. 1) The CF, RC, and frequency variable RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the remote control receiver circuit On-chip Debugger * Supports software debugging with the IC mounted on the target board. Package Form * QIP100E(14x20): Lead-free type * TQFP100(14x14): Lead-free type (Under Development) Development Tools * On-chip debugger: TCB87-TypeB + LC87F7DJ2B or TCB87 TypeC(3Lines Cable) + LC87F7DJ2B Flash ROM Programming Boards
Package QIP100E(14x20) TQFP100(14x14) Programming boards W87FQ100 W87FSQ100
Flash ROM Programmer
Maker Model AF9708 Single AF9709/AF9709B/AF9709C (Including product of Ando Electric Co., Ltd) Flash Support Group, Inc. (FSG) Gang AF9723/AF9723B(Main body) (Including product of Ando Electric Co., Ltd) AF9833(Unit) (Including product of Ando Electric Co., Ltd) Flash Support Group, Inc. (FSG) + SANYO (Note 1) Single/Gang SANYO Onboard Single/Gang Onboard Single/Gang AF9101/AF9103(Main body) (FSG) SIB87(interface driver) (SANYO) SKK/SKK Type B (SANYO FWS) SKK-DBG Type B (SANYO FWS) Application Version After 1.05 Chip Data Version After 2.23 LC87F7DJ2B (Note 2) LC87F7DJ2B (Note 2) (Note 2) LC87F7DJ2B (Note 2) LC87F7DJ2B Supported version Device
Note 1: With the FSG onboard programmer (AF9101/AF9103) and the serial interface driver provided by SANYO, PC-less standalone onboard programming is possible Note 2: Depending on programming conditions, it is necessary to use a dedicated programming device and a program. Please contact SANYO or FSG if you have any questions or difficulties regarding this matter.
No.A1636-5/26
LC87F7DJ2B
Package Dimensions
unit : mm (typ) 3151A
23.2 80 81 51 50
0.8 14.0
20.0
100 1 0.65 (0.58)
(2.7)
31 30 0.3 0.15
3.0max
0.1
SANYO : QIP100E(14X20)
Package Dimensions
unit : mm (typ) 3274
16.0 14.0 75 76 51 50
[Under Development]
17.2
0.5
100 1 (1.0)
(1.0)
26 0.5 0.2 25 0.125
1.2max
0.1
SANYO : TQFP100(14X14)
14.0 16.0
No.A1636-6/26
Pin Assignments
V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/UTX2/S52 P35/INT5/T1IN/URX2/S53 P00/DGBP0 P01/DGBP1 P02/DGBP2 P03/INT6 P04/INT7 P05/CKO 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
LC87F7DJ2B
LC87F7DJ2B
SANYO: QIP100E(14x20)
Top view
P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN P73/INT3/T0IN/RMIN S0/PA0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
V3/PL6/AN14/DBGP2 S47/PF7/INT7 S46/PF6/INT6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S23/PC7 S22/PC6 S21/PC5
"Lead-free Type"
No.A1636-7/26
S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1
LC87F7DJ2B
S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 VSS2 VDD2 S47/PF7 V3/PL6/AN14/DBGP2 V2/PL5/AN13/DBGP1 V1/PL4/AN12/DBGP0 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/INT4/T1IN/INT6/T0LCP1/PWM4/S48 P31/INT4/T1IN/PWM5/S49 VSS3 VDD3 P32/INT4/T1IN/UTX1/S50 P33/INT4/T1IN/URX1/S51 P34/INT5/T1IN/INT7/T0HCP1/S52 P35/INT5/T1IN/S52 P00/DGBP0 P01/DGBP1 P02/T8LO/DGBP2 P03/T8HO P04 P05/CKO P06/T6O P07/T7O P10/SO0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
LC87F7DJ2B
S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN
P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7/MICIN P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/NKIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Top view
SANYO: TQFP100(14x14) "Lead-free Type" (Under Development)
No.A1636-8/26
LC87F7DJ2B
System Block Diagram
Interrupt control
IR
PLA
Standby control Flash ROM CF RC VMRC X'tal Clock generator
PC
ACC
B register
C register
ALU SIO0 SIO1 Timer 0 (High speed clock counter) Timer 1 Base timer LCD Controller INT0 to 7 Noise Rejection Filter Timer 4 Timer 5 UART1 PWM4/5 Remote control receiver circuit 1 Remote control receiver circuit 2 Bus interface Port 0 Port 1 Port 3 RAR Port 7 Port 8 ADC Stack pointer Small signal detector Timer 6 UART2 On-chip debugger Timer 7 Timer 8 Day and time counter Watchdog timer RAM PSW
No.A1636-9/26
LC87F7DJ2B
Pin Description
Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Port 0 P00 to P07 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Input for HOLD release * Input for port 0 interrupt * Shared pins P03: INT6 input P04: INT7 input P05: Clock output (system clock/can selected from sub clock) P06: Timer 6 toggle output P07: Timer 7 toggle output On chip debugger pins: DBGP0 to DBGP2(P00 to P02) Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Port 3 P30 to P35 I/O * 6-bit I/O port * Segment output for LCD * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P30 to P33: INT4 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P34 to P35: INT5 input/HOLD release input/timer 1 event input/timer 0L capture input/ timer 0H capture input P30: PWM4 output/INT6 input/timer 0L capture 1 input P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit/INT7 input/timer 0H capture 1 input P35: UART2 receive Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising & Falling enable enable enable enable H level disable disable disable disable L level disable disable disable disable Yes Yes Yes I/O - power supply pin Description Option No
-
+ power supply pin
No
Continued on next page.
No.A1636-10/26
LC87F7DJ2B
Continued from preceding page.
Pin Name Port 7 P70 to P73 I/O I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 * 8-bit I/O port * I/O specifiable in 1-bit units * Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) S0/PA0 to S7/PA7 S8/PB0 to S15/PB7 S16/PC0 to S23/PC7 S24/PD0 to S31/PD7 S32/PE0 to S39/PE7 S40/PF0 to S47/PF7 I/O I/O I/O I/O I/O I/O * Segment output for LCD * Can be used as general-purpose I/O port (PA) * Segment output for LCD * Can be used as general-purpose I/O port (PB) * Segment output for LCD * Can be used as general-purpose I/O port (PC) * Segment output for LCD * Can be used as general-purpose I/O port (PD) * Segment output for LCD * Can be used as general-purpose I/O port (PE) * Segment output for LCD * Can be used as general-purpose I/O port (PF) PF6: INT6 input PF7: INT7 input COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 I/O I/O * Common output for LCD * Can be used as general-purpose input port (PL) * LCD output bias power supply * Can be used as general-purpose input port (PL) * Shared pins AD converter input ports: AN12 (V1) to AN14 (V3) On-chip debugger pins: DBGP0 (V1) to DBGP2 (V3) RES XT1 Input Input Reset pin * 32.768kHz crystal oscillator input pin * Shared pins General-purpose input port AD converter input port: AN10 XT2 I/O Must be connected to VDD1 if not to be used. * 32.768kHz crystal oscillator output pin * Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No No No No No No No No No No No enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable Description Option No
Port 8 P80 to P87
I/O
No
No.A1636-11/26
LC87F7DJ2B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P00 to P07 Option Selected in Units of each bit Option Type 1 2 P10 to P17 each bit 1 2 P30 to P35 each bit 1 2 P70 P71 to P73 P80 to P87 S0/PA0 to S47/PF7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 XT1 XT2 No No No Input only Input only Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No No No No No No No No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS Nch-open drain CMOS Input only Output Type Pull-up Resistor Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable No Programmable No
User Option List
Option Name Option Type Mask Version *1 Flash Version Option Selected in Units of each bit CMOS Nch-open drain Port output form P10 to P17 each bit CMOS Nch-open drain P30 to P35 Program start address x *2 each bit CMOS Nch-open drain 00000H 1FF00H Specified item
P00 to P07
*1: Mask option selection - No change possible after the mask is completed. *2: Program start address of the mask version is 00000h.
LSI VDD1 Power supply
For backup *2
VDD2 VDD3
VSS1
VSS2 VSS3
*1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. *2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A1636-12/26
LC87F7DJ2B
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Maximum supply voltage supply voltage for LCD Input voltage VI(1) VI(2) Input/output voltage VIO(1) VLCD V1/PL4, V2/PL5, V3/PL6 Port L XT1, CF1, RES VDD2, VDD3 Ports 0, 1, 3, 7, 8 Ports A, B, C Ports D, E, F XT2 Peak output current IOPH(2) IOPH(3) IOPH(4) Mean output High level output current current (Note 1-1) IOMH(2) IOMH(3) IOMH(4) Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) Peak output current IOPL(1) IOPL(2) IOPL(3) IOPL(4) Mean output Low level output current current (Note 1-1) IOML(1) IOML(2) IOML(3) IOML(4) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) Maximum power dissipation Pd max Ports 30, 31 Ports 71 to 73 Ports A, B, C Ports D, E, F Ports 0, 1, 32 to 35 Ports 30, 31 Ports 0, 1, 3 Ports 71 to 73 Ports A, B, C Ports D, E, F Ports A, B, C Ports D, E, F Ports 0, 1, 32 to 35 Ports 30, 31 Ports 7, 8 XT2 Ports A, B, C Ports D, E, F Ports 0, 1, 32 to 35 Ports 30, 31 Ports 7, 8 XT2 Ports A, B, C Ports D, E, F Ports 0, 1, 32 to 35 Ports 30, 31 Ports 0, 1, 3 Ports 7, 8 XT2 Ports A, B, C Ports D, E, F Ports A, B, C Ports D, E, F QIP100E(14x20) TQFP100(14x14) Ta=-40 to +85C Ta=-40 to +85C mW Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Current at each pin Current at each pin Current at each pin Current at each pin Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins Total of all pins IOMH(1) Ports 30, 31 Ports 71 to 73 Ports A, B, C Ports D, E, F Ports 0, 1, 32 to 35 * CMOS output selected * Current at each pin * CMOS output selected * Current at each pin Current at each pin Current at each pin IOPH(1) Ports 0, 1, 32 to 35 * CMOS output selected * Current at each pin * CMOS output selected * Current at each pin Current at each pin Current at each pin -10 -20 -5 -5 -7.5 -15 -3 -3 -25 -25 -45 -5 -25 -25 -45 20 30 10 10 15 20 7.5 7.5 45 45 80 20 45 45 80 -0.3 VDD+0.3 VDD1=VDD2=VDD3 Symbol VDD max Pin/Remarks VDD1, VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 -0.3 VSS Specification typ max +6.5 VDD VDD+0.3 VDD+0.1 unit
V
mA
Note 1-1: The mean output current is a mean value measured over 100ms.
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LC87F7DJ2B
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Parameter Operating ambient temperature Storage ambient temperature Tstg Symbol Topr Pin/Remarks Conditions VDD[V] min -40 -55 Specification typ max +85 C +125 unit
Allowable Operating Range at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage (Note 2-1) Memory sustaining supply voltage High level input voltage VIH(2) VIH(1) Ports 0, 3, 8 Ports A, B, C, D, E, F Port L Port 1 Ports 71 to 73 P70 port input/ interrupt side VIH(3) VIH(4) VIH(5) VIH(6) Low level input voltage VIL(1) P71 interrupt side P87 small signal input side P70 watchdog timer side XT1,XT2,CF1, RES Ports 0, 3, 8 Ports A, B, C, D, E, F Port L VIL(2) Port 1 Ports 71 to 73 P70 port input/ interrupt side VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) CF1 * CF2 pin open * System clock frequency division ratio=1/1 * External system clock duty=505% * CF2 pin open * System clock frequency division ratio=1/2 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 0.2 0.2 0.2 30 16 8 2.2 to 5.5 0.1 4 MHz tCYC P71 interrupt side P87 small signal input side P70 watchdog timer side XT1, XT2, CF1, RES Output disabled * Output disabled * When INT1VTSL=1 Output disabled * Output disabled * When INT1VTSL=0 (P71 only) Output disabled Output disabled * Output disabled * When INT1VTSL=1 Output disabled 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 2.2 to 4.0 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 0.85VDD 0.75VDD 0.9VDD 0.75VDD VSS VSS VSS VSS VSS VSS VSS VSS 0.190 0.356 0.712 0.1 0.1 VDD VDD V VDD VDD 0.15VDD +0.4 0.2VDD 0.1VDD +0.4 0.2VDD 0.45VDD 0.25VDD 0.8VDD -1.0 0.25VDD 200 200 200 15 8 s * Output disabled * When INT1VTSL=0 (P71 only) 2.2 to 5.5 0.3VDD +0.7 VDD Output disabled 2.2 to 5.5 0.3VDD +0.7 VDD Symbol VDD(1) VDD(2) VDD(3) VHD VDD1 Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.190s tCYC 200s 0.356s tCYC 200s 0.712s tCYC 200s RAM and register contents sustained in HOLD mode. 2.0 5.5 min 3.0 2.5 2.2 Specification typ max 5.5 5.5 5.5 unit
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2.
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No.A1636-14/26
LC87F7DJ2B
Continued from preceding page.
Parameter Oscillation frequency range (Note 2-3) FmCF(3) FmRC FmVMRC(1) CF1, CF2 FmCF(2) CF1, CF2 Symbol FmCF(1) Pin/Remarks CF1, CF2 Conditions VDD[V] * 15MHz ceramic oscillation * See Fig. 1. * 8MHz ceramic oscillation * See Fig. 1. * 4MHz ceramic oscillation * See Fig. 1. Internal RC oscillation * Frequency variable RC source oscillation * When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=0 FmVMRC(2) * Frequency variable RC source oscillation * When VMRAJ2 to 0=4, VMFAJ2 to 0=0, VMSL4M=1 FsX'tal Frequency variable RC oscillation usable range Frequency variable RC oscillation adjustment range VmADJ(2) VmADJ(1) Each step of VMRAJn (Wide range) Each step of VMFAJn (Small range) 2.2 to 5.5 1 4 8 2.2 to 5.5 8 24 64 % OpVMRC(1) OpVMRC(2) XT1, XT2 * 32.768kHz crystal oscillation * See Fig. 2. When VMSL4M=0 When VMSL4M=1 2.2 to 5.5 3.5 4 4.5 2.2 to 5.5 2.2 to 5.5 8 32.768 10 12 MHz kHz 2.2 to 5.5 4 MHz 2.2 to 5.5 10 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 0.3 min Specification typ 15 8 4 1.0 2.0 max unit
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 3, 7, 8 Ports A, B, C Ports D, E, F Port L IIH(2) IIH(3) IIH(4) IIH(5) RES XT1, XT2 CF1 P87 small signal input side Low level input current IIL(1) Ports 0, 1, 3, 7, 8 Ports A, B, C Ports D, E, F Port L IIL(2) IIL(3) IIL(4) IIL(5) RES XT1, XT2 CF1 P87 small signal input side Conditions VDD[V] * Output disabled * Pull-up resistor off * VIN=VDD (Including output Tr's off leakage current) VIN=VDD * For input port specification * VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS: Bias voltage) * Output disabled * Pull-up resistor off * VIN=VSS (Including output Tr's off leakage current) VIN=VSS * For input port specification * VIN=VSS VIN=VSS VIN=VBIS-0.5V (VBIS: Bias voltage) 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 2.2 to 4.5 -1 -1 -15 -15 -10 -8.5 -5.5 -4.2 -1.5 2.2 to 5.5 -1 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 4.5 to 5.5 2.2 to 4.5 4.2 1.5 8.5 5.5 1 1 15 15 10 A 2.2 to 5.5 1 min Specification typ max unit
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No.A1636-15/26
LC87F7DJ2B
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Parameter High level output voltage Symbol VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) VOH(9) VOH(10) VOH(11) Low level output voltage VOL(1) VOL(2) VOL(3) Ports 0, 1, 32 to 35 Ports 30,31 (PWM function output mode) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) VOL(9) VOL(10) LCD output voltage regulation VODLS Ports 30, 31 (Port function output mode) Ports 7, 8 XT2 Ports A, B, C Ports D, E, F S0 to S53 IOL=30mA IOL=5mA IOL=2.5mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA * IO=0mA * VLCD, 2/3VLCD,1/3VLCD level output * See Fig. 8. VODLC COM0 to COM3 * IO=0mA * VLCD, 2/3VLCD,1/2VLCD, 1/3VLCD level output * See Fig. 8. LCD bias resistor RLCD(1) RLCD(2) Resistance per one bias resister Resistance per one bias resister 1/2 mode Resistance of pull-up MOS Tr. Hysterisis voltage Rpu(1) Rpu(2) VHYS(1) VHYS(2) Pin capacitance CP Ports 0, 1, 3, 7 Ports A, B, C Ports D, E, F Ports 1, 7 RES P87 small signal input side All pins * For pins other than that under test: VIN=VSS * f=1MHz * Ta=25C Input sensitivity Vsen P87 small signal input side 2.2 to 5.5 0.12VDD Vp-p 2.2 to 5.5 10 pF 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 18 50 0.1VDD V 0.1VDD 150 VOH=0.9VDD 4.5 to 5.5 15 35 80 See Fig. 8. 2.2 to 5.5 30 k See Fig. 8. 2.2 to 5.5 60 2.2 to 5.5 0 0.2 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 1.5 0.4 0.4 0.4 0.4 0.4 0.4 Ports A, B, C Ports D, E, F Ports 71 to 73 Ports 30, 31 Pin/Remarks Ports 0, 1, 32 to 35 IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOL=10mA IOL=1.6mA IOL=1mA 2.2 to 5.5 0.4 V Conditions VDD[V] 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 min VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 Specification typ max unit
2.2 to 5.5
0
0.2
No.A1636-16/26
LC87F7DJ2B
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/reception mode Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.2 to 5.5 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) tdD0(3) (Note 4-1-3) 2.2 to 5.5 (1/3)tCYC +0.05 2.2 to 5.5 2.2 to 5.5 0.03 2.2 to 5.5 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 1tCYC +0.05 s
Serial output
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
Output clock
No.A1636-17/26
LC87F7DJ2B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.2 to 5.5 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 0.03 2.2 to 5.5 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 2.2 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) Conditions VDD[V] See Fig. 6. min 2 2.2 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Serial clock
s
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P30 to P33), INT5(P34 to P35), INT6(P30), INT7(P34) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIH(6) tPIL(6) tPIL(7) RES RMIN(P73) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 MICIN(P87) * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. Condition that signal is accepted to small signal detection counter. Condition that signal is accepted to remote control receiver circuit. Resetting is enabled. 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 1 4 200 RMCK (Note5-1) s 2.2 to 5.5 256 2.2 to 5.5 64 2.2 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 min Specification typ max unit
Note 5-1: RMCK is an unit for the base clock (40tCYC/50tCYC/Sub-Clock) of remote control receiver circuit.
No.A1636-18/26
LC87F7DJ2B
AD Converter Characteristics at VSS1 = VSS2 = VSS3 =0V
<12bits AD Converter Mode at Ta =-20 to +70C>
Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS -1 VAIN tCAD N ET Symbol Pin/Remarks AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) * See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 55.6 VSS 115 VDD 1 V A (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 32 115 min Specification typ 12 max unit bit LSB
s
<8bits AD Converter Mode at Ta =-30 to +70C>
Parameter Resolution Absolute accuracy Conversion time Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN TCAD N ET Symbol Pin/Remarks AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) * See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 -1 34.27 VSS 90 VDD 1 (Note 6-1) Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 20 min Specification typ 8 1.5 90 s max unit bit LSB
V A
12bits AD Converter Mode: TCAD(Conversion time)=((52/(division ratio)) + 2) x (1/3) xtCYC 8bits AD Converter Mode: TCAD(Conversion time)=((32/(division ratio)) + 2) x (1/3) xtCYC
External oscillation FmCF [MHz] 12 15 Operating supply voltage range VDD [V] 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 System division ratio (SYSDIV) 1/1 1/1 1/1 Cycle time tCYC [ns] 250 250 200 AD division ratio (ADDIV) 1/8 1/16 1/16 12bit AD 34.8 69.5 55.6 AD conversion time (tCAD) [s] 8bit AD 21.5 42.8 34.27
Note 6-1: The quantization error (1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: * The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. * The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
No.A1636-19/26
LC87F7DJ2B
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=15MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 8MHz side * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * FmCF=4MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 4MHz side * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped. IDDOP(13) * System clock set to 10MHz with frequency variable RC oscillation * 1/1 frequency division ratio IDDOP(14) IDDOP(15) IDDOP(16) IDDOP(17) IDDOP(18) IDDOP(19) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped. * System clock set to 4MHz with frequency variable RC oscillation * 1/1 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio 2.2 to 3.0 13.0 43.3 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 1.7 32.8 17.4 3.5 128.7 56.9 A 4.5 to 5.5 3.0 to 3.6 3.25 2.1 11.5 6.6 3.0 to 3.6 4.3 12.0 4.5 to 5.5 6.5 20.0 2.2 to 3.0 0.3 1.35 3.0 to 3.6 0.4 1.7 4.5 to 5.5 3.0 to 3.6 2.5 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 6.1 4.0 3.0 2.1 2.0 1.7 0.7 15.0 8.8 6.8 8.7 5.3 4.4 3.1 3.0 to 3.6 5.6 12.0 4.5 to 5.5 8.7 23.7 min Specification typ max unit
mA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
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No.A1636-20/26
LC87F7DJ2B
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Parameter HALT mode consumption current (Note 7-1) IDDHALT(2) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 * HALT mode * FmCF=15MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(3) * HALT mode * FmCF=8MHz ceramic oscillation mode IDDHALT(4) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 8MHz side * Internal RC oscillation stopped. IDDHALT(5) * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(6) * HALT mode * FmCF=4MHz ceramic oscillation mode IDDHALT(7) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 4MHz side * Internal RC oscillation stopped. IDDHALT(8) * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDHALT(9) IDDHALT(10) IDDHALT(11) IDDHALT(12) * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode IDDHALT(13) * Internal RC oscillation stopped. * System clock set to 10MHz with frequency variable RC oscillation * 1/1 frequency division ratio IDDHALT(14) * HALT mode * FmCF=0Hz (oscillation stopped) IDDHALT(15) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped. * System clock set to 4MHz with IDDHALT(16) frequency variable RC oscillation * 1/1 frequency division ratio IDDHALT(17) * HALT mode * FmCF=0Hz (oscillation stopped) IDDHALT(18) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal RC oscillation stopped. IDDHALT(19) * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) * Timer HOLD mode * CF1=VDD or open (External clock mode) * FmX'tal=32.768kHz crystal oscillation mode 2.2 to 3.0 3.6 24.6 VDD1 * HOLD mode * CF1=VDD or open (External clock mode) 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 3.0 to 3.6 0.14 0.030 0.025 15.5 6.3 38.8 18.4 14.0 91.0 34.4 A 2.2 to 3.0 4.8 27.3 3.0 to 3.6 7.7 48.1 4.5 to 5.5 18.6 207.8 2.2 to 3.0 0.6 1.2 3.0 to 3.6 0.7 1.75 4.5 to 5.5 1.3 3.5 3.0 to 3.6 1.6 4.6 4.5 to 5.5 2.6 7.7 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 0.3 0.18 0.14 1.3 0.75 0.54 2.2 to 3.0 0.5 1.3 mA 3.0 to 3.6 0.7 1.8 4.5 to 5.5 1.3 3.9 2.5 to 3.0 1.0 2.5 3.0 to 3.6 1.3 3.1 4.5 to 5.5 2.2 6.2 3.0 to 3.6 2.2 11.9 4.5 to 5.5 3.6 21.8 Conditions VDD[V] min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
No.A1636-21/26
LC87F7DJ2B
F-ROM Write Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = VSS3 = 0V
Parameter Onboard programming current Programming time tFW(1) * 128-byte programming * Erasing current included * Time for setting up 128-byte data is excluded. 3.0 to 5.5 22.5 45 ms Symbol IDDFW(1) Pin/Rem arks VDD1 Conditions VDD[V] * 128-byte programming * Erasing current included 3.0 to 5.5 25 40 mA min Specification typ max unit
UART (Full Duplex) Operating Conditions at Ta = -40 to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Transfer ate Symbol UBR Pin/Remarks UTX(P32), URX(P33) Conditions VDD[V] 2.2 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC
Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit Receive data (LSB first) End of reception
Start bit Start of reception
UBR
No.A1636-22/26
LC87F7DJ2B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] C2 [pF] Rf1 [] Rd1 [] Operating Voltage Range [V] Oscillation Stabilization Time typ [ms] max [ms] Remarks
15MHz
MURATA
CSTCE15M0V53-R0
(15)
(15)
Open
220
2.8 to 5.5
0.05
0.15
12MHz
MURATA
CSTCE12M0G52-R0
(10)
(10)
Open
470
2.8 to 5.5
0.05
0.15
CSTCE8M00G52-R0 8MHz MURATA CSTLS8M00G52-B0 CSTCR4M00F53-R0 4MHz MURATA CSTLS4M0053-B0
(10) (15) (15) (15)
(10) (15) (15) (15)
Open Open Open Open
680 2.5 to 5.5 15k 2.2k 2.2 to 5.5 2.2k
0.05 0.05 0.05 0.05
0.15 0.15 0.15 0.15
Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator Values shown in parentheses are capacitance included in the oscillator
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency Vendor Name EPSON TOYOCOM Oscillator Name C3 [pF] 32.768kHz MC-306 18 Circuit Constant C4 [pF] 18 Rf2 [] Open Rd2 [] 560k Operating Voltage Range [V] 2.0 to 5.5 Oscillation Stabilization Time typ [s] 1.4 max [s] 3.0 Applicable CL value =12.5pF Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf1
Rd1
Rf2
Rd2
C1 CF
C2
C3 X'tal
C4
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
No.A1636-23/26
LC87F7DJ2B
0.5VDD
Figure 3 AC Timing Measurement Point
VDD Operating VDD lower limit 0V Reset time RES
Power supply
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal VALID
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times
No.A1636-24/26
LC87F7DJ2B
VDD
RRES
RES CRES
Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the IC's operating voltage.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (SIO0 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1636-25/26
LC87F7DJ2B
VDD SW : ON/OFF (programmable)
RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND SW: ON (VLCD=VDD)
Figure 8 LCD Bias Resistor
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This catalog provides information as of December, 2009. Specifications and information herein are subject to change without notice.
PS No.A1636-26/26

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